Multi-port memories provide independent data channels enabling a read or a write on each channel to addresses asynchronously from each other. For illustration, one port of a memory cell, such as a port P_A, is write accessed while another port of the same cell, such as a port P_B, is dummy read accessed. A dummy read refers to a situation in which signals for the memory cell are in a read condition but the data on a port for reading is not reliable and is thus not used. Generally, the dummy read from port P_B increases a load on a storage node of the memory cell to be written by port P_A, and thus prolongs the write time from port P_A. Stated differently, the write from port P_A is write disturbed by port P_B. In many situations, effects of the load from the dummy read from port P_B are worse when the dummy read from port P_B starts before the write from port P_A, compared with the situation where the write from port P_A starts before the dummy read from port P_B, for example.
One solution to improve the write disturb to port P_A is to increase the clock cycle and thus increase write timing margins for port P_A. Alternatively and/or additionally, the write drivers for port P_A are strengthened. However, such a solution results in slow cycle times, larger areas for the strong write drivers, and increased power consumption. Another solution is to restrict dual port accesses to preclude port P_A and port P_B addressing the same row, which is restrictive and is not useful in many applications.
Like reference symbols in the various drawings indicate like elements.